1. Field of the Invention
The present invention relates to a method of controlling a page buffer having a dual register and a control circuit thereof. More specifically, the present invention relates to a method of controlling a page buffer having a dual register in which the entire program time can be reduced through reduction in a program time upon normal program, and a control circuit thereof.
2. Discussion of Related Art
Recently, there is an increasing demand for semiconductor memory devices that can be electrically programmed and erased and do not require a refresh function to rewrite data in a predetermined period. Further, in order to develop a large-capacity memory device in which lots of data can be stored, research has been actively made into high-integration technology of the memory device. In the above, the program refers to an operation for writing data into a memory cell and the erasure refers to an operation for erasing data written in the memory cell.
For higher-integration of a memory device, a NAND-type flash memory device in which a plurality of memory cells are serially connected (i.e., a structure in which neighboring cells share drain or source) to constitute one string was developed. The NAND-type flash memory device is a memory device that reads information sequentially unlike a NOR-type flash memory device. Program and erasure of this NAND-type flash memory device are performed by controlling the threshold voltage of the memory cell while injecting or discharging electrons into or from a floating gate through the F-N tunneling method.
The NAND-type flash memory device employs a page buffer in order to store a large capacity of information within a short time. The page buffer provides a large quantity of data received from an input/output pad I/O PAD to the memory cells. The page buffer typically consists of a single register in order to temporarily store data. Recently, however, the page buffer is composed of a dual register in order to increase the program speed upon large-capacity data program in the NAND-type flash memory device.
For example, a conventional page buffer having the dual register is shown in FIG. 4. In FIG. 4, reference numerals P1 to P4 indicate a PMOS transistor, N1 to N18 indicates a NMOS transistor, and HN1 to HN4 indicates a high voltage NMOS transistor.
Referring to FIG. 4, the conventional page buffer having the dual register performs a program operation on memory cells of a memory cell array 10 according to data received from the I/O pad during a program operation. This page buffer includes a cache register 23, and a main register 22 that stores data received from the cache register 23 and provides the data to the memory cell array 10 depending upon the operation of a bit line select unit 21.
The operational properties when the page buffer shown in FIG. 4 performs the program operation will now be described.
During the program operation, a node passing through a pad YA is grounded. In this state, if ‘1’ data is received from the input/output pad, a control signal DI1 being a data-in signal is activated. Thus, transistors N13 and N14 are turned on and an input terminal Qab of a latch unit 231 of the cache register 23 thus shifts to a LOW level. On the contrary, if ‘0’ data is received from the input/output pad, a control signal nDI being a data-in signal is activated. Thus, a transistor N15 is turned on and an output terminal QA of the latch unit 231 of the cache register 23 shifts to a LOW level. In other words, according to data received from the input/output pad, data having a given value is stored in the latch unit 231 of the cache register 23 and is transmitted to the main register 22 via a node SD through a transistor N16 that is turned-on by a control signal PDUMP. Then, the data is stored in a latch unit 221. The data stored in the latch unit 221 of the main register 22 is transmitted to the plurality of the memory cells of the memory cell array 10 through a bit line select unit 21, so that the program operation is performed.
In the conventional page buffer shown in FIG. 4, the above-mentioned operation is performed in the same manner upon normal program as well as a cache program. Generally, the program operation can be divided into the normal program and the cache program in which data is stored in the cache register 23 in advance and the program is then performed in order to increase the program speed. In this time, the normal program refers to a program operation wherein a data program is performed once. The cache program refers to a program operation in which a program should be performed consecutively several times. Generally, during the normal program operation, a normal program command signal indicating a program operation command signal, an address signal, data and a normal program operation are inputted to the input/output pad. On the contrary, during the cache program operation, a cache program command signal indicating a program operation command signal, an address signal, data and a cache program operation are inputted to the input/output pad. That is, the normal program and the cache program are divided through the normal program command signal and the cache program command signal.
As described above, in the conventional page buffer, during the normal program and the cache program operation, a process in which data is transferred to the main register 22 via the cache register 23 and is then transmitted to the memory cell array 10 is performed. In other words, during all the program operations (including the normal program and cache program), a process in which data is transferred from the cache register 23 to the main register 22 is carried out. Time taken to transmit data from the cache register 23 to the main register 22 is approximately 3 μs. Of course, the program speed can be increased in the case of the cache program using the cache register 22 that is used to program a large capacity of data. However, there is a problem in that a transfer time needed for transmitting data from the cache register 23 to the main register 22 is unnecessarily consumed in the case of the normal program.